library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( R : in std_logic_vector (7 downto 0);
S : in std_logic_vector (7 downto 0);
Cin: in std_logic;
operacion: in std_logic_vector (2 downto 0);
F : out std_logic_vector (7 downto 0);
boverflow : out std_logic;
bsigno : out std_logic;
bcero : out std_logic;
bacarreo :out std_logic;
Z: buffer std_logic_vector (7 downto 0));

end ALU;

architecture Behavioral of ALU is
constant s0 : std_logic_vector(7 downto 0) := B"00000000";

begin

process (R,S,operacion)
begin
if operacion = "000"
then F <= R+S; 
     Z <= R+S;
end if; 
end process;

process (Z,R,S)
begin
bcero <= '0'; 
bsigno <= '0';
boverflow <= '0';

if Z = "00000000"
then bcero <= '1';
end if;



if (R(7)='0' and S(7)='0' and Z(7)='1') or (R(7)='1' and S(7)='1' and Z(7)='0')
then boverflow <= '1';
	  bsigno <= '0';
elsif Z(7) = '1' 
     then bsigno <= '1';
end if;


end process;


end Behavioral;